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DATE
2002
IEEE
135views Hardware» more  DATE 2002»
13 years 9 months ago
Reducing Test Application Time Through Test Data Mutation Encoding
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...
Sherief Reda, Alex Orailoglu
ASPDAC
2004
ACM
151views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Combinatorial group testing methods for the BIST diagnosis problem
— We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vector...
Andrew B. Kahng, Sherief Reda
ISPD
2005
ACM
249views Hardware» more  ISPD 2005»
13 years 10 months ago
APlace: a general analytic placement framework
We streamline and extend APlace, the general analytic placement engine based on ideas of Naylor et al. [7] and described in [3, 4, 5]. Previous work explored the adaptability of A...
Andrew B. Kahng, Sherief Reda, Qinke Wang
ISPD
2005
ACM
153views Hardware» more  ISPD 2005»
13 years 10 months ago
Evaluation of placer suboptimality via zero-change netlist transformations
In this paper we introduce the concept of zero-change transformations to quantify the suboptimality of existing placers. Given a netlist and its placement from a placer, we formal...
Andrew B. Kahng, Sherief Reda
ISPD
2005
ACM
188views Hardware» more  ISPD 2005»
13 years 10 months ago
A semi-persistent clustering technique for VLSI circuit placement
Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for a significant p...
Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, S...