FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs

This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliability of commercial electronics. For the first time, a fast and accurate methodology FASER based on static, vector-less analysis of error rates due to single event upsets in general combinational circuits is proposed. Accurate models are based on STA-like pre-characterization methods, and logical masking is computed via binary decision diagrams with circuit partitioning. Experimental results indicate that FASER achieves good accuracy compared to the SPICE-based simulation method. The average error across the benchmark circuits is 12% at over 90,000X speed-up. The accuracy can be further improved by more accurate cell library characterization. The run-time for ISCAS’85 benchmark circuits ranges from 10 to 120 minutes. The estimated bit error rate (BER) for the ISCAS’85 benchmark circuits implemented in the ...

• Type: Conference
• Year: 2006
• Where: ISQED
• Authors: Bin Zhang, Wei-Shen Wang, Michael Orshansky
• Keywords: Benchmark Circuits, Combinational Circuits, Hardware, ISQED 2006, Single Event Upsets