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GLVLSI
2003
IEEE
187views VLSI» more  GLVLSI 2003»
9 years 4 months ago
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology
Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou...
GLVLSI
2003
IEEE
239views VLSI» more  GLVLSI 2003»
9 years 4 months ago
CMOS flash analog-to-digital converter for high speed and low voltage applications
A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flas...
Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi
GLVLSI
2003
IEEE
145views VLSI» more  GLVLSI 2003»
9 years 4 months ago
Using dynamic domino circuits in self-timed systems
We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit i...
Jung-Lin Yang, Erik Brunvand
GLVLSI
2003
IEEE
147views VLSI» more  GLVLSI 2003»
9 years 4 months ago
Clustering based acyclic multi-way partitioning
In this paper, we present a clustering based algorithm for acyclic multi-way partitioning. Many existing partitioning algorithms have shown that clustering can effectively improv...
Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei M...
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
9 years 4 months ago
A comprehensive high-level synthesis system for control-flow intensive behaviors
Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, L...
GLVLSI
2003
IEEE
175views VLSI» more  GLVLSI 2003»
9 years 4 months ago
A custom FPGA for the simulation of gene regulatory networks
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
Ilias Tagkopoulos, Charles A. Zukowski, German Cav...
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
9 years 4 months ago
Information storage capacity of crossbar switching networks
In this work we ask the fundamental question: How many bits of information can be stored in a crossbar switching network? The answer is trivial when the switches of the network ar...
Paul-Peter Sotiriadis
GLVLSI
2003
IEEE
195views VLSI» more  GLVLSI 2003»
9 years 4 months ago
A pipelined clock-delayed domino carry-lookahead adder
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
Bhushan A. Shinkre, James E. Stine
GLVLSI
2003
IEEE
194views VLSI» more  GLVLSI 2003»
9 years 4 months ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu...
GLVLSI
2003
IEEE
186views VLSI» more  GLVLSI 2003»
9 years 4 months ago
A fast simulation approach for inductive effects of VLSI interconnects
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...
Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-D...
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