Exploiting compiler-generated schedules for energy savings in high-performance processors

This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors with out-of-order issue logic. In this HybridScheduling paradigm, regions of the application containing large amounts of parallelism visible at compile-time completely bypass the dynamic scheduling logic and execute in a low power static mode. Simulation studies using the Wattch framework on several media and scientific benchmarks demonstrate large improvements in overall energy consumption of 43% in kernels and 25% in full applications with only a 2.8% performance degradation on average. Categories and Subject Descriptors C.1 [Processor Architectures]: RISC/CISC, VLIW Architectures General Terms Performance, Design Keywords Low Energy, Instruction-Level Parallelism, Dynamic Issue Processors, Very Long Instruction Word Architectures

• Type: Conference
• Year: 2003
• Where: ISLPED
• Authors: Madhavi Gopal Valluri, Lizy Kurian John, Heather Hanson
• Keywords: Dynamic Scheduling, Dynamic Scheduling Logic, ISLPED 2003, Modern Superscalar Processors