IC Analyses Including Extracted Inductance Models

IC inductance extraction generally produces either port inductances based on simplified current path assumptions or a complete partial inductance matrix. Combining either of these results with the IC interconnect resistance and capacitance models significantly complicates most IC design and verification methodologies. In this tutorial paper we will review some of the analysis and verification problems associated with on–chip inductance, and present a subset of recent results for partially addressing the challenges which lie ahead. Keywords Interconnect; Inductance; Model Order Reduction.

• Type: Conference
• Year: 1999
• Where: DAC
• Authors: Michael W. Beattie, Lawrence T. Pileggi
• Keywords: Complete Partial Inductance, Computer Architecture, DAC 1999, IC Inductance Extraction, IC Interconnect Resistance