Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

4

ISLPED
1998
ACM

favoriteEmaildiscussreport

75views Hardware» more ISLPED 1998»

A power optimization method considering glitch reduction by gate sizing

13 years 8 months ago

A power optimization method considering glitch reduction by gate sizing

Download www.cecs.uci.edu

Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta

Real-time Traffic

Hardware | ISLPED 1998 |

claim paper

Related Content

» A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design

» Soft ErrorAware Power Optimization Using Gate Sizing

» General Methodology for SoftErrorAware Power Optimization Using Gate Sizing

» Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages

» A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

» Flipflop insertion with shiftedphase clocks for FPGA power reduction

» Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

» Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program

» Leakage poweraware clock skew scheduling converting stolen time into leakage power reducti...

Post Info
More Details (n/a)

Added	05 Aug 2010
Updated	05 Aug 2010
Type	Conference
Year	1998
Where	ISLPED
Authors	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru

Comments (0)