20 search results - page 1 / 4 » A power optimization method considering glitch reduction by ... |
ISLPED
1998
ACM
13 years 9 months ago
1998
ACM
DAC
1999
ACM
14 years 5 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
PATMOS
2007
Springer
13 years 11 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
TCAD
2008
13 years 4 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...