Incremental elaboration for run-time reconfigurable hardware designs

We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific integrated circuits (ASICs) or microprocessors. These systems can often provide substantially more computational power than microprocessors and support higher flexibility than ASICs. The compilation of hardware during run time, however, can add significant runtime overhead to these systems. We introduce a novel compilation technique called incremental elaboration, which enables circuits to be dynamically generated during run time. We propose a set-based model for incremental elaboration, and explain how it can be used in the hardware compilation process. Our approach is illustrated by various designs, particulary those for pattern matching and shape-adaptive template matching. Categories and Subject Descriptors B.5.1 [Register-Transfer-Level Implementation]: Design--Special-purpose Genera...

• Type: Conference
• Year: 2006
• Where: CASES
• Authors: Arran Derbyshire, Tobias Becker, Wayne Luk
• Keywords: CASES 2006, Hardware Compilation, Incremental Elaboration, Run-time Reconfigurable Hardware, System Software