Pattern matching in reconfigurable logic for packet classification

We describe a digital circuit synthesis algorithm specialized for the domain of pattern matching circuits implemented in reconfigurable logic. We propose to use this algorithm as part of a system for implementing high-throughput pattern classification, for instance as part of a packet filter in an internetwork router. The goals of the approach are throughputs on the order of 100M classifications per second with reconfiguration times (including all synthesis) being held to a minimum. We evaluate the algorithms using rulesets from a pattern classification problem in networking, IP firewalling (150 rules on 100 bits), and evaluate their fitness to handle the demands placed on them by high-speed networks. In addition we use synthetic rulesets in an attempt to explore the scalability of our algorithm.

• Type: Conference
• Year: 2001
• Where: CASES
• Authors: Adam Johnson, Kenneth Mackenzie
• Keywords: CASES 2001, Circuit Synthesis Algorithm, Pattern Classification, Pattern Matching Circuits, System Software