Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

5

ASPDAC
1995
ACM

favoriteEmaildiscussreport

93views Hardware» more ASPDAC 1995»

Architectural simulation for a programmable DSP chip set

13 years 8 months ago

Architectural simulation for a programmable DSP chip set

Download www.cecs.uci.edu

Jong Tae Lee, Jaemin Kim, Jae Cheol Son

Real-time Traffic

ASPDAC 1995 | Hardware |

claim paper

Related Content

» LISA Machine Description Language for CycleAccurate Models of Programmable DSP Architectu...

» Rapid Prototyping for Configurable SystemonaChip Platforms A Simulation Based Approach

» A GALS manycore heterogeneous DSP platform with sourcesynchronous onchip interconnection n...

» A Low Area and Low Power Programmable Baseband Processor Architecture

» Addressing the SystemonaChip Interconnect Woes Through CommunicationBased Design

» Characterizing processor architectures for programmable network interfaces

» Architecture of Embedded Video Processing in a Multimedia ChipSet

» Benchmarkbased design strategies for single chip heterogeneous multiprocessors

» Evolution of Analog Circuits on Field Programmable Transistor Arrays

Post Info
More Details (n/a)

Added	25 Aug 2010
Updated	25 Aug 2010
Type	Conference
Year	1995
Where	ASPDAC
Authors	Jong Tae Lee, Jaemin Kim, Jae Cheol Son

Comments (0)