Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, H...
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
Jens Bieger, Sorin A. Huss, Michael Jung, Stephan ...
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...