An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design

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An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25k gate CMOS Test Chip has been designed, manufactured (5491 devices), and evaluated with over 300 tests. The chip contains five types of CUTs derived from functions in production ASICs.

Piero Franco, William D. Farwell, Robert L. Stokes

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CMOS Test Chip | Combinational Circuits | Hardware | ITC 1995 | Multiple Testing Techniques |

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Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1995
Where	ITC
Authors	Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey

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An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design

CMOS Test Chip | Combinational Circuits | Hardware | ITC 1995 | Multiple Testing Techniques |

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