Performance space modeling for hierarchical synthesis of analog integrated circuits

Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, in terms of both performance estimation and hierarchical design optimization method. This paper discusses and compares recent developments in this area, with special emphasis on automated modeling and on multi–objective bottom–up hierarchical design. Categories and Subject Descriptors J.6 [Computer-Aided Engineering]: Computer-aided design; I.6.5 [Simulation and Modeling]: Model Development—Modeling methodologies General Terms Algorithms, Design, Performance Keywords Hierarchical Synthesis

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert
• Keywords: Analog Design Productivity, Computer Architecture, DAC 2005, Hierarchical Design, Hierarchical Design Optimization