Design Alternatives for Parallel Saturating Multioperand Adders

Parallel saturating multioperand adders significantly improve the performance of GSM speech coders by giving compilers and assembly language programmers the ability to parallelize loops containing saturating dot products, while maintaining GSM compliant results. This paper presents four designs for parallel saturating multioperand adders. These designs have at most one carry-propagate adder on their critical delay path, yet produce the same results that would be obtained if the additions were performed serially with saturation after each addition. The four parallel designs offer tradeoffs in terms of area, worst case delay, and dot product latency. Compared to a 5-input serial design, the 5-input parallel designs have delays up to 3.51 times shorter.

• Type: Conference
• Year: 2001
• Where: ICCD
• Authors: Pablo I. Balzola, Michael J. Schulte, Jie Ruan, C. John Glossner, Erdem Hokenek
• Keywords: 5-input Parallel Designs, Designs Offer Tradeoffs, Hardware, ICCD 2001, Parallel Designs