9 search results - page 1 / 2 » Design Alternatives for Parallel Saturating Multioperand Add... |
CASES
2000
ACM
13 years 10 months ago
2000
ACM
This paper presents designs for parallel saturating multioperand adders. These adders have only a single carrypropagate adder on the critical delay path, yet produce the same resu...
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
Parallel saturating multioperand adders significantly improve the performance of GSM speech coders by giving compilers and assembly language programmers the ability to paralleliz...
ARITH
2009
IEEE
14 years 17 days ago
2009
IEEE
The design of a component to perform parallel addition of multiple floating-point (FP) operands is explored in this work. In particular, a 3-input FP adder is discussed in more d...
ASAP
2002
IEEE
13 years 10 months ago
2002
IEEE
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be sup...
GLVLSI
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC o...