A low-power FPGA based on autonomous fine-grain power-gating

— This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell efficiently, asynchronous architecture is full exploited. The proposed FPGA is fabricated in a 90nm CMOS process with dual threshold voltages. It is more efficient in power than the synchronous FPGA at less than 30% utilization.

• Type: Conference
• Year: 2009
• Where: ASPDAC
• Authors: Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
• Keywords: ASPDAC 2009, Dual Threshold Voltages, FPGA, Hardware, first Implementation