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ASPDAC
2005
ACM

Analysis of buffered hybrid structured clock networks

10 years 3 months ago
Analysis of buffered hybrid structured clock networks
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical analysis methods to reduce the circuit complexity and speedup the simulation. A simple controlled sources model is used for modeling clock buffers to deal with nonlinearity in the buffered clock trees. Our experiment results show that the proposed algorithm is about two orders of magnitude faster than HSPICE without loss on accuracy and stability. The relatively errors on delay times are within a few percent of the exact ones.
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld
Added 13 Oct 2010
Updated 13 Oct 2010
Type Conference
Year 2005
Where ASPDAC
Authors Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
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