DFT
1997
IEEE
13 years 9 months ago
1997
IEEE
Recent increases in the density and size of memory ICs made it ne cessary to search for new defect tolerance techniques since the traditional methods are no longer e ective enough...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...