Block placement to ensure channel routability

Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total width/height of the chip and optimal routing area can be obtained. The proposed technique utilizes a piecewise linear model of the channel width. Based on this model, we introduce LP formulation to determine the optimal channel width considering pin alignment by balancing the wire length and the channel width. Categories and Subject Descriptors: B.7.2 [Design Aids]: Placement and Routing General Terms: Algorithms

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh
• Keywords: Channel Width, GLVLSI 2007, Optimal Channel Width, Optimal Routing Area, VLSI