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GLVLSI
2009
IEEE

On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design

8 years 10 months ago
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design
This paper discusses the impact of migrating from 2-D to 3-D on floorplanning and placement. By looking at a basic formulation of graph cuboidal dual problem, we show that the 3-D case and the 3-layer 2.5-D case are fundamentally more difficult than the 2-D case in terms of computational complexity. By comparison among these cases, the intrinsic complexity in 3-D floorplan structures is revealed in the hard-deciding relations between topological connections and geometrical contacts. The results show future challenges for physical design and CAD of 3-D integrated circuits. Categories and Subject Descriptors J.6 [Computer Applications]: Computer-aided design General terms – Algorithms, theory Keywords – 3-D integrated circuits, cuboidal dual, computational complexity
Renshen Wang, Chung-Kuan Cheng
Added 21 May 2010
Updated 21 May 2010
Type Conference
Year 2009
Where GLVLSI
Authors Renshen Wang, Chung-Kuan Cheng
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