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GLVLSI
2009
IEEE
159views VLSI» more  GLVLSI 2009»
13 years 11 months ago
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design
This paper discusses the impact of migrating from 2-D to 3-D on floorplanning and placement. By looking at a basic formulation of graph cuboidal dual problem, we show that the 3-...
Renshen Wang, Chung-Kuan Cheng
GLVLSI
2006
IEEE
165views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Block alignment in 3D floorplan using layered TCG
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S...
ICCAD
2007
IEEE
124views Hardware» more  ICCAD 2007»
14 years 1 months ago
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. ...