Sciweavers

Share
DAC
2007
ACM

Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations

11 years 3 months ago
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations
Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis has become essential. We present a novel method for post-silicon analysis that gathers data from a small number of on-chip test structures, and combines this information with pre-silicon statistical timing analysis to obtain narrow, die-specific, timing PDFs. Experimental results show that for the benchmark suite being considered, taking all parameter variations into consideration, our approach can get a PDF with the standard deviation 83.5% smaller on average than the SSTA result. The approach is scalable to smaller test structure overheads. Categories and Subject Descriptors B.7.2 [B.7.3]: Integrated CircuitsDesign Aids, Redundant Design General Terms Performance, Design Keywords Post-Silicon Optimization, Statistical Timing Analysis
Qunzeng Liu, Sachin S. Sapatnekar
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2007
Where DAC
Authors Qunzeng Liu, Sachin S. Sapatnekar
Comments (0)
books