A design flow for protecting FPGA-based systems against single event upsets

SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarks circuits and on a realistic circuit to show the capabilities of the proposed design flow.

• Type: Conference
• Year: 2005
• Where: DFT
• Authors: Luca Sterpone, Massimo Violante
• Keywords: Design Flow, DFT 2005, Hardware, Programmable Gate Arrays, Single Event Upsets