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2002
IEEE

Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures

9 years 8 months ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreover, dynamically reconfigurable logic (DRL) architectures are an exciting alternative for embedded systems design. However, all previous approaches to DRL multi-context scheduling and HW/SW scheduling for DRL architectures are based on static scheduling techniques. In this paper, we address this problem and present: (1) a dynamic scheduler hardware architecture, and (2) four dynamic run-time scheduling algorithms for DRL-based multi-context platforms. The scheduling algorithms have been integrated in our codesign environment, where a large number of experiments have been carried out. Results demonstrate the benefits of our approach. Keywords Dynamic run-time scheduling, reconfigurable architectures.
Juanjo Noguera, Rosa M. Badia
Added 14 Jul 2010
Updated 14 Jul 2010
Type Conference
Year 2002
Where CODES
Authors Juanjo Noguera, Rosa M. Badia
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