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2009
IEEE

An ILP formulation for task mapping and scheduling on multi-core architectures

9 years 3 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory architecture, and task mapping and scheduling. This paper presents an integer linear programming formulation for the task mapping and scheduling problem. The technique incorporates profiling-driven loop level task partitioning, task transformations, functional pipelining, and memory architecture aware data mapping to reduce system execution time. Experiments are conducted to evaluate the technique by implementing a series of DSP applications on several multi-core architectures based on dynamically reconfigurable processor cores. The results demonstrate that the proposed technique is able to generate high-quality mappings of realistic applications on the target
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan
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