An embedded true random number generator for FPGAs

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An embedded true random number generator for FPGAs
Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. In this paper we extend a technique that uses on-chip jitter and PLLs to a much larger class of FPGAs that do not contain PLLs. Our design uses only the Configurable Logic Blocks (CLBs) common to all FPGAs, and has a self-testing capability. Using the intrinsic jitter contained in digital circuits, we produce random bits at speeds of up to 0.5 Mbits/second with good statistical characteristics. We discuss the engineering challenges of extracting random bits from digital circuits, and we report the results of running standard statistical tests (NIST) on the output generated by our system. Categories and Subject Descriptors G.3 [Probability and Statistics]: Random Number Generation; E.3 [Data Encryption]. General Terms Algorithms, Design, Experimentatio...
Paul Kohlbrenner, Kris Gaj
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where FPGA
Authors Paul Kohlbrenner, Kris Gaj
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