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2007
IEEE

High Level Synthesis of Degradable ASICs Using Virtual Binding

11 years 11 months ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to develop techniques for reusing faulty dies, even with a degraded performance. In this paper, a new method for high level synthesis of degradable ASICs is presented. Our technique introduces the concept of Virtual Binding. In this approach, the operations are bound to virtual components that are linked with actual non-faulty components using a set of configuration multiplexers and flip-flops embedded in the data-path. Using virtual components simplifies the synthesis algorithm and decreases the size of generated control unit. Virtual-to-physical mapping of the components will be established by programming the configuration flip-flops after diagnosing the faulty components. The experimental results show that the area and delay overhead of the resulting circuits have acceptable values compared to the original, n...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where VTS
Authors Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi
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