Sciweavers

Share
VTS
2007
IEEE
114views Hardware» more  VTS 2007»
9 years 5 months ago
Parameter Estimation for a Model with Both Imperfect Test and Repair
We describe estimation of the parameters of a manufacturing test and repair model using data available from that test. The model allows imperfect testing and imperfect repair. The...
Simon P. Wilson, Ben Flood, Suresh Goyal, Jim Mosh...
VTS
2007
IEEE
79views Hardware» more  VTS 2007»
9 years 5 months ago
Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression
A methodology is presented for improving the amount of compression achieved by continuous-flow decompressors by using multiple ratios of scan chains to tester channels (i.e., expa...
Richard Putman, Nur A. Touba
VTS
2007
IEEE
95views Hardware» more  VTS 2007»
9 years 5 months ago
Delay Test Quality Evaluation Using Bounded Gate Delays
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Soumitra Bose, Vishwani D. Agrawal
VTS
2007
IEEE
103views Hardware» more  VTS 2007»
9 years 5 months ago
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
VTS
2007
IEEE
100views Hardware» more  VTS 2007»
9 years 5 months ago
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology
In this paper, we identify two main bottlenecks in the functional diagnosis flow and propose new ways to overcome these. Our approach completely eliminates the “Primary Input (P...
Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srik...
VTS
2007
IEEE
116views Hardware» more  VTS 2007»
9 years 5 months ago
Case Study: Soft Error Rate Analysis in Storage Systems
Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. In this paper we analyze the soft error vulnerability of FPGAs used in storage systems. Sinc...
Brian Mullins, Hossein Asadi, Mehdi Baradaran Taho...
VTS
2007
IEEE
135views Hardware» more  VTS 2007»
9 years 5 months ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud...
VTS
2007
IEEE
85views Hardware» more  VTS 2007»
9 years 5 months ago
Minimizing the Impact of Scan Compression
Peter Wohl, John A. Waicukauski, Rohit Kapur, S. R...
VTS
2007
IEEE
105views Hardware» more  VTS 2007»
9 years 5 months ago
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
Attack resistance has been a critical concern for security-related applications. Various side-channel attacks can be launched to retrieve security information such as encryption k...
Chunsheng Liu, Yu Huang
books