16 search results - page 1 / 4 » Joint Minimization of Power and Area in Scan Testing by Scan... |
ISVLSI
2003
IEEE
13 years 9 months ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce b...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
VTS
2008
IEEE
13 years 11 months ago
2008
IEEE
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...