67 search results - page 1 / 14 » Low power synthesis of dual threshold voltage CMOS VLSI circ... |
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...