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2010

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

8 years 10 months ago
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.
Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimo
Added 30 Jan 2011
Updated 30 Jan 2011
Type Journal
Year 2010
Where TCAD
Authors Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue
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