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ATS
2010
IEEE
229views Hardware» more  ATS 2010»
9 years 9 months ago
Variation-Aware Fault Modeling
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
Fabian Hopsch, Bernd Becker, Sybille Hellebrand, I...
TCAD
2008
98views more  TCAD 2008»
9 years 11 months ago
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
Khaled R. Heloue, Farid N. Najm
TCAD
2008
136views more  TCAD 2008»
9 years 11 months ago
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst-case design scheme, but it reduces the pessimism involved i...
Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar
CORR
2007
Springer
95views Education» more  CORR 2007»
9 years 11 months ago
Parametric Yield Analysis of Mems via Statistical Methods
This paper considers a developing theory on the effects of inevitable process variations during the fabrication of MEMS and other microsystems. The effects on the performance and ...
Shyam Praveen Vudathu, Kishore K. Duganapalli, Rai...
FTEDA
2006
137views more  FTEDA 2006»
9 years 11 months ago
Statistical Performance Modeling and Optimization
As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing process...
Xin Li, Jiayong Le, Lawrence T. Pileggi
ISLPED
2010
ACM
170views Hardware» more  ISLPED 2010»
9 years 12 months ago
Low-power sub-threshold design of secure physical unclonable functions
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depen...
Lang Lin, Daniel E. Holcomb, Dilip Kumar Krishnapp...
DAC
2005
ACM
10 years 1 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
10 years 1 months ago
Process variation robust clock tree routing
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
Wai-Ching Douglas Lam, Cheng-Kok Koh
DATE
2004
IEEE
120views Hardware» more  DATE 2004»
10 years 3 months ago
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...
Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
ICCAD
2007
IEEE
134views Hardware» more  ICCAD 2007»
10 years 3 months ago
Efficient decoupling capacitance budgeting considering operation and process variations
This paper solves the variation-aware on-chip decoupling capacitance (decap) budgeting problem. Unlike previous work assuming the worst-case current load, we develop a novel stocha...
Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He
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