Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

9

DAC
1997
ACM

favoriteEmaildiscussreport

93views Computer Architecture» more DAC 1997»

Post-Layout Logic Restructuring for Performance Optimization

13 years 9 months ago

Post-Layout Logic Restructuring for Performance Optimization

Download cadlab.ece.ucsb.edu

Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Mal

Real-time Traffic

Computer Architecture | DAC 1997 |

claim paper

Related Content

» Joint logic restructuring and pin reordering against NBTIinduced performance degradation

» Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring

» Multiplexer restructuring for FPGA implementation cost reduction

» Layout Driven Logic RestructuringDecomposition

» Delay driven AIG restructuring using slack budget management

» Node addition and removal in the presence of dont cares

» CircuitBased Preprocessing of ILP and Its Applications in Leakage Minimization and Power E...

» The ins and outs of gradual type inference

» Dynamically Optimizing HighDimensional Index Structures

Post Info
More Details (n/a)

Added	06 Aug 2010
Updated	06 Aug 2010
Type	Conference
Year	1997
Where	DAC
Authors	Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska

Comments (0)