10 search results - page 1 / 2 » Post-Layout Logic Restructuring for Performance Optimization |
DAC
1997
ACM
13 years 10 months ago
1997
ACM
DATE
2009
IEEE
14 years 18 days ago
2009
IEEE
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal re...
TCAD
2008
13 years 5 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
ICCAD
1991
IEEE
13 years 9 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...