Sciweavers

Share
CASES
2015
ACM

Scheduling instruction effects for a statically pipelined processor

3 years 5 months ago
Scheduling instruction effects for a statically pipelined processor
Statically pipelined processors have a fully exposed datapath where all portions of the pipeline are directly controlled by effects within an instruction, which simplifies hardware and enables a new level of compiler optimizations. This paper describes an effect scheduling strategy to aggressively compact instructions, which has a critical impact on code size and performance. Unique scheduling challenges include more frequent name dependences and fewer renaming opportunities due to static pipeline (SP) registers being dedicated for specific operations. We also realized the SP in a hardware implementation language (VHDL) to evaluate the real energy benefits. Despite the compiler challenges, we achieve performance, code size, and energy improvements compared to a conventional MIPS processor. Keywords compiler, architecture, static pipeline, performance, energy
Added 17 Apr 2016
Updated 17 Apr 2016
Type Journal
Year 2015
Where CASES
Comments (0)
books