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ACSD
2010
IEEE
224views Hardware» more  ACSD 2010»
9 years 9 months ago
Robustness of Sequential Circuits
Digital components play a central role in the design of complex embedded systems. These components are interconnected with other, possibly analog, devices and the physical environm...
Laurent Doyen, Thomas A. Henzinger, Axel Legay, De...
ISLPED
2000
ACM
92views Hardware» more  ISLPED 2000»
10 years 3 months ago
Low power sequential circuit design by using priority encoding and clock gating
This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
Xunwei Wu, Massoud Pedram
ICCAD
1996
IEEE
121views Hardware» more  ICCAD 1996»
10 years 3 months ago
Identification of unsettable flip-flops for partial scan and faster ATPG
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
ICCD
1997
IEEE
100views Hardware» more  ICCD 1997»
10 years 3 months ago
Optimal Clock Period Clustering for Sequential Circuits with Retiming
Abstract— In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock perio...
Arvind K. Karandikar, Peichen Pan, C. L. Liu
DATE
1999
IEEE
111views Hardware» more  DATE 1999»
10 years 4 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Jaan Raik, Raimund Ubar
ATS
2000
IEEE
145views Hardware» more  ATS 2000»
10 years 4 months ago
Compaction-based test generation using state and fault information
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwa...
EH
2002
IEEE
104views Hardware» more  EH 2002»
10 years 4 months ago
Evolvable Hardware for the Generation of Sequential Filter Circuits
Evolutionary algorithms (EAs) are regularly used both for the solution of scheduling problems, and for the creation of digital circuit designs. This paper describes a unified app...
Robert Thomson, Tughrul Arslan
DAC
2006
ACM
10 years 5 months ago
Mining global constraints for improving bounded sequential equivalence checking
In this paper, we propose a novel technique on mining relationships in a sequential circuit to discover global constraints. In contrast to the traditional learning methods, our mi...
Weixin Wu, Michael S. Hsiao
DFT
2007
IEEE
104views VLSI» more  DFT 2007»
10 years 6 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
DATE
2007
IEEE
154views Hardware» more  DATE 2007»
10 years 6 months ago
Soft error rate analysis for sequential circuits
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...
Natasa Miskov-Zivanov, Diana Marculescu
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