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DAC
1996
ACM

Sizing of Clock Distribution Networks for High Performance CPU Chips

10 years 3 months ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a complex grid with multiple drivers. The large capacitance of this distribution grid together with the high clock frequency results in substantial power dissipation in the chip. In this paper, we describe techniques to size the interconnect segments (thus reducing their capacitance) of the distribution network while meeting certain design goals. These techniques place no restrictions on the topology of the network being sized, and have been successfully used on very large examples.
Madhav P. Desai, Radenko Cvijetic, James Jensen
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1996
Where DAC
Authors Madhav P. Desai, Radenko Cvijetic, James Jensen
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