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CSREAESA
2004

A Distributed FIFO Scheme for System on Chip Inter-Component Communication

8 years 11 months ago
A Distributed FIFO Scheme for System on Chip Inter-Component Communication
Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as fast as the devices. Scaling implies that complete systems can now be built on a single chip, requiring long interconnects for global signals and clock distribution networks. We propose having distributed first in first out buffers to facilitate communication between components/modules of highly integrated systems, such as system on chip. Using first in first out buffers will alleviate the clock skew, clock distribution and single clock synchronization problems; all of which are a result of global interconnect delays. In this paper, we present simple buffer circuitry and the associated control circuits that
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut
Added 30 Oct 2010
Updated 30 Oct 2010
Type Conference
Year 2004
Where CSREAESA
Authors Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias
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