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2005
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Soft Error Mitigation for SRAM-Based FPGAs

12 years 7 months ago
Soft Error Mitigation for SRAM-Based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped design. Moreover, the number of sensitive configuration bits is two orders of magnitude more than user bits in typical FPGA-based circuits. In this paper, we present a high-reliable low-cost mitigation technique which can significantly improve the availability of designs mapped into FPGAs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increases to more than 99%.
Ghazanfar Asadi, Mehdi Baradaran Tahoori
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where VTS
Authors Ghazanfar Asadi, Mehdi Baradaran Tahoori
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