Sciweavers

Share
ICCAD
2003
IEEE

A Statistical Gate-Delay Model Considering Intra-Gate Variability

10 years 4 months ago
A Statistical Gate-Delay Model Considering Intra-Gate Variability
This paper proposes a model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability. As the variation of individual gate delays directly influences the circuitdelay variation, it is important to characterize each gate-delay variation accurately. Furthermore, as every transistor in a gate affects the transient characteristics of the gate, it is also necessary to consider the intra-gate variability in the model of gate-delay variation. This effect is not captured in existing statistical delay analyses. The proposed model considers the intra-gate variability through the introduction of sensitivity constants. The accuracy of the model is evaluated, and some simulation results for circuit delay variation are presented.
Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2003
Where ICCAD
Authors Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera
Comments (0)
books