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TCAD
2002
73views more  TCAD 2002»
10 years 2 months ago
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource c...
Vikram Iyengar, Krishnendu Chakrabarty
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
10 years 6 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
10 years 6 months ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy
ATS
2001
IEEE
137views Hardware» more  ATS 2001»
10 years 6 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu
DDECS
2009
IEEE
149views Hardware» more  DDECS 2009»
10 years 6 months ago
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
Yiorgos Sfikas, Yiorgos Tsiatouhas
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
10 years 7 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
DFT
2002
IEEE
117views VLSI» more  DFT 2002»
10 years 8 months ago
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
Ozgur Sinanoglu, Alex Orailoglu
DATE
2002
IEEE
117views Hardware» more  DATE 2002»
10 years 8 months ago
Effective Software Self-Test Methodology for Processor Cores
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning tech...
Nektarios Kranitis, Antonis M. Paschalis, Dimitris...
ATS
2002
IEEE
108views Hardware» more  ATS 2002»
10 years 8 months ago
Fault Set Partition for Efficient Width Compression
In this paper, we present a technique for reducing the test length of counter-based pseudo-exhaustive built-in self-testing (BIST) based on width compression method. More formally...
Emil Gizdarski, Hideo Fujiwara
VTS
2003
IEEE
122views Hardware» more  VTS 2003»
10 years 8 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
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