12 search results - page 1 / 3 » Thermal-aware Steiner routing for 3D stacked ICs |
NOCS
2010
IEEE
13 years 3 months ago
2010
IEEE
—Three-dimensional network-on-chip (3D NoC), the combination of NoC and die-stacking 3D IC technology, is motivated to achieve lower latency, lower power consumption, and higher ...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— In this paper, we present the first work on the Steiner routing for 3D stacked ICs. In the 3D Steiner routing problem, the pins are located in multiple device layers, which ma...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
- 3D IC technologies can help to improve circuit performance and lower power consumption by reducing wirelength. Also, 3D IC technology can be used to realize heterogeneous system-...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
ISPD
2012
ACM
12 years 3 days ago
2012
ACM
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...