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ISCA
2010
IEEE
413views Hardware» more  ISCA 2010»
13 years 10 months ago
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
Xiaochen Guo, Engin Ipek, Tolga Soyata
ISCA
2010
IEEE
405views Hardware» more  ISCA 2010»
13 years 10 months ago
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU
Recent advances in computing have led to an explosion in the amount of data being generated. Processing the ever-growing data in a timely manner has made throughput computing an i...
Victor W. Lee, Changkyu Kim, Jatin Chhugani, Micha...
ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
13 years 10 months ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 10 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
ISCA
2010
IEEE
314views Hardware» more  ISCA 2010»
13 years 10 months ago
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis
Power consumption has become a major constraint in the design of processors today. To optimize a processor for energyefficiency requires an examination of energy-performance trade...
Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay...
Hardware
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