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ISPD
2010
ACM
249views Hardware» more  ISPD 2010»
14 years 5 days ago
A matching based decomposer for double patterning lithography
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
Yue Xu, Chris Chu
ISPD
2010
ACM
244views Hardware» more  ISPD 2010»
14 years 5 days ago
Completing high-quality global routes
Jin Hu, Jarrod A. Roy, Igor L. Markov
ISPD
2010
ACM
224views Hardware» more  ISPD 2010»
14 years 5 days ago
An analytical placer for mixed-size 3D placement
Existing 3D placement techniques are mainly used for standardcell circuits, while mixed-size placement is needed to support highlevel functional units and intellectual property (I...
Jason Cong, Guojie Luo
ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
14 years 5 days ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...
ISPD
2010
ACM
207views Hardware» more  ISPD 2010»
14 years 5 days ago
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this paper we present FOARS, ...
Gaurav Ajwani, Chris Chu, Wai-Kei Mak
Hardware
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