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» 3D floorplanning with thermal vias
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ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 2 months ago
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
Madhubanti Mukherjee, Ranga Vemuri
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
14 years 2 months ago
Simultaneous power and thermal integrity driven via stapling in 3D ICs
The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first ...
Hao Yu, Joanna Ho, Lei He
ASPDAC
2006
ACM
166views Hardware» more  ASPDAC 2006»
13 years 11 months ago
Temperature-aware routing in 3D ICs
Three-dimensional integrated circuits (3D ICs) provide an attractive solution for improving circuit performance. Such solutions must be embedded in an electrothermally-conscious d...
Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar
ISPD
2005
ACM
151views Hardware» more  ISPD 2005»
13 years 11 months ago
Thermal via placement in 3D ICs
As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promi...
Brent Goplen, Sachin S. Sapatnekar
ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
13 years 7 months ago
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs
: Thermal issue is a critical challenge in 3D IC circuit design. Incorporating thermal vias into 3D IC is a promising way to mitigate thermal issues by lowering down the thermal re...
Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jas...