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DATE
2009
IEEE
149views Hardware» more  DATE 2009»
13 years 11 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
IPPS
2006
IEEE
13 years 11 months ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
ICC
2007
IEEE
132views Communications» more  ICC 2007»
13 years 8 months ago
Supporting Bulk Data Transfers of High-End Applications with Guaranteed Completion Time
In high-end grid networks, distributed resources (scientific instruments, CPUs, storages, etc.) are interconnected to support computing-intensive and data-intensive applications, w...
Bin Bin Chen, Pascale Vicat-Blanc Primet
DAC
2006
ACM
14 years 5 months ago
Leakage power reduction of embedded memories on FPGAs through location assignment
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
Yan Meng, Timothy Sherwood, Ryan Kastner
CASES
2001
ACM
13 years 8 months ago
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
Girish Venkataramani, Walid A. Najjar, Fadi J. Kur...