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DAC
2005
ACM
14 years 6 months ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
DAC
2002
ACM
14 years 6 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
ICS
2007
Tsinghua U.
13 years 11 months ago
GridRod: a dynamic runtime scheduler for grid workflows
Grid Workflows are emerging as practical programming models for solving large e-scientific problems on the Grid. However, it is typically assumed that the workflow components eith...
Shahaan Ayyub, David Abramson
FPGA
2008
ACM
184views FPGA» more  FPGA 2008»
13 years 6 months ago
Mapping for better than worst-case delays in LUT-based FPGA designs
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
Kirill Minkovich, Jason Cong
GLVLSI
2007
IEEE
171views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Combinational equivalence checking for threshold logic circuits
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevo...