52 search results - page 2 / 11 » A Design-for-Testability Technique for Detecting Delay Fault... |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
DFT
2002
IEEE
13 years 10 months ago
2002
IEEE
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
IFIP
2001
Springer
13 years 9 months ago
2001
Springer
: High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single In...