Sciweavers

28 search results - page 2 / 6
» A Detailed Router for Field-Programmable Gate Arrays
Sort
View
FPL
2006
Springer
161views Hardware» more  FPL 2006»
13 years 9 months ago
Predictive Load Balancing for Interconnected FPGAs
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...
Jason D. Bakos, Charles L. Cathey, Allen Michalski
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
13 years 10 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
FPL
2004
Springer
87views Hardware» more  FPL 2004»
13 years 11 months ago
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
This paper presents an innovative way to deploy Bitstream Intellectual Property (BIP) cores. By using standard tools to generate bitstreams for Field Programmable Gate Arrays (FPGA...
Edson L. Horta, John W. Lockwood
FCCM
2009
IEEE
123views VLSI» more  FCCM 2009»
13 years 9 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
Hoang Le, Viktor K. Prasanna
FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
14 years 13 days ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna