116 search results - page 2 / 24 » A High-level Interconnect Power Model for Design Space Explo... |
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
A tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time OTA-C filter when given only high-level input parameters such as dynamic ...
DATE
2009
IEEE
14 years 6 days ago
2009
IEEE
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constr...
VLSID
2009
IEEE
14 years 6 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
— With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems....
DATE
2008
IEEE
13 years 12 months ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...